Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor
US11201152B2 · kind B2 · utility
8Cited by
4References
5Claims
0Family size
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Key dates
| Filing date | Apr 20, 2018 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Aug 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.