Method for manufacturing a structure for forming a tridimensional monolithic integrated circuit
US11205702B2 · kind B2 · utility
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1References
18Claims
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Key dates
| Filing date | Mar 31, 2017 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83894
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.