Reverse contact and silicide process for three-dimensional logic devices

US11264274B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Jeffrey Smith · Clifton Park, US
• Hiroaki Niimi · Cohoes, US
• Jodi Grzeskowiak · Albany, US
• Daniel Chanemougame · Niskayuna, US
• Lars Liebmann · Poughquag, US
• Kandabara Tapily · Mechanicville, US
• Subhadeep Kal · Albany, US
• Anton J. deVilliers · Boise, US

Key dates

• Filing date: Sep 2, 2020
• Grant date: Mar 1, 2022
• Expiry date: Sep 2, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.