Conductive lines with subtractive cuts
US11276639B2 · kind B2 · utility
2Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Apr 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated chips and methods of forming lines in the same include forming a line layer on a substrate. An opening is etched into the line layer that exposes the substrate. A plug is formed in the opening. The line layer is patterned to form a line that terminates at the plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.