Managing low-level instructions and core interactions in multi-core processors
US11327759B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2018 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Sep 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/301
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction. The second high-level instruction occurs after the first high-level instruction within a series of high-level instructions, and delaying insertion of the low-level instruction provided for performing the operation into an insertion position within the series of low-level instructions, where the delaying causes the insertion position to be between a final low-level instruction converted from the first high-level instruction and an initial low-level instruction converted from the second high-level instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.