Stacked transistor structures with asymmetrical terminal interconnects

US11342227B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Ehren Mannebach · Beaverton, US
• Nafees Kabir · Portland, US
• Patrick Morrow · Portland, US
• Gilbert Dewey · Beaverton, US
• Willy Rachmady · Beaverton, US
• Anh Phan · Beaverton, US

Key dates

• Filing date: Mar 27, 2020
• Grant date: May 24, 2022
• Expiry date: Mar 27, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0142
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension.