Weight prefetch for in-memory neural network execution
US11347994B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2018 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Apr 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/251
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.