Instructions and logic to perform floating point and integer operations for machine learning

US11360767B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Himanshu Kaul · Portland, US
• Mark A. Anders · Hillsboro, US
• Sanu K. Mathew · Hillsboro, US
• Anbang Yao · Beijing, CN
• Joydeep Ray · Folsom, US
• Ping T. Tang · Edison, US
• Michael S. Strickland · Sunnyvale, US
• Xiaoming Chen · Xi'an, CN
• Tatiana Shpeisman · Menlo Park, US
• Abhishek R. Appu · Cameron Park, US
• Altug Koker · Cameron Park, US
• Kamal Sinha · Rancho Cordova, US
• Balaji Vembu · Folsom, US
• Nicolas C. Galoppo Von Borries · Portland, US
• Eriko Nurvitadhi · Beaverton, US
• Rajkishore Barik · Santa Clara, US
• Tsung-Han Lin · Campbell, US
• Vasanth Ranganathan · Cameron Park, US
• Sanjeev Jahagirdar · Folsom, US

Key dates

• Filing date: Jul 6, 2021
• Grant date: Jun 14, 2022
• Expiry date: Jul 6, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/005
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.