Stacked nanowire transistor structure with different channel geometries for stress

US11367722B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Stephen M. Cea · Hillsboro, US
• Gilbert Dewey · Beaverton, US
• Willy Rachmady · Beaverton, US
• Roza Kotlyar · Portland, US
• Rishabh Mehandru · Portland, US
• Sean T. Ma · Portland, US
• Ehren Mannebach · Beaverton, US
• Anh Phan · Beaverton, US
• Cheng-Ying Huang

Key dates

• Filing date: Sep 21, 2018
• Grant date: Jun 21, 2022
• Expiry date: Oct 22, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.