Low power ferroelectric based majority logic gate multiplier
US11381244B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Dec 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/938
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.