Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

US11393818B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Gilbert Dewey · Beaverton, US
• Ravi Pillarisetty · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Aaron D. Lilak · Beaverton, US
• Willy Rachmady · Beaverton, US
• Rishabh Mehandru · Portland, US
• Kimin Jun · Hillsboro, US
• Anh Phan · Beaverton, US
• Hui Jae Yoo · Hillsboro, US
• Patrick Morrow · Portland, US
• Cheng-Ying Huang

Key dates

• Filing date: Mar 28, 2018
• Grant date: Jul 19, 2022
• Expiry date: Jul 5, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).