Low synch dedicated accelerator with in-memory computation capability

US11416165B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Amrita Mathuriya · Portland, US
• Sasikanth Manipatruni · Ithaca, US
• Victor W. Lee · Santa Clara, US
• Huseyin Ekin Sumbul · Portland, US
• Gregory K. Chen · Ann Arbor, US
• Raghavan Kumar · Hillsboro, US
• Phil Knag · Portland, US
• Ram Krishnamurthy · Portland, US
• Ian A. Young · Portland, US
• Abhishek A. Sharma · Hillsboro, US

Key dates

• Filing date: Oct 15, 2018
• Grant date: Aug 16, 2022
• Expiry date: May 29, 2041

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.