Majority logic gate having paraelectric input capacitors and a local conditioning mechanism
US11418197B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2021 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | May 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.