Self-aligned local interconnects

US11424160B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Ehren Mannebach · Beaverton, US
• Anh Phan · Beaverton, US
• Richard E. Schenker · Portland, US
• Stephanie A. Bojarski · Beaverton, US
• Willy Rachmady · Beaverton, US
• Patrick Morrow · Portland, US
• Jeffery D. Bielefeld · Forest Grove, US
• Gilbert Dewey · Beaverton, US
• Hui Jae Yoo · Hillsboro, US
• Nafees Kabir · Portland, US

Key dates

• Filing date: Feb 13, 2019
• Grant date: Aug 23, 2022
• Expiry date: Dec 23, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0158
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.