In-memory analog neural cache

US11502696B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Amrita Mathuriya · Portland, US
• Sasikanth Manipatruni · Ithaca, US
• Victor W. Lee · Santa Clara, US
• Huseyin Ekin Sumbul · Portland, US
• Gregory K. Chen · Ann Arbor, US
• Raghavan Kumar · Hillsboro, US
• Phil Knag · Portland, US
• Ram Krishnamurthy · Portland, US
• Ian A. Young · Portland, US
• Abhishek A. Sharma · Hillsboro, US

Key dates

• Filing date: Oct 15, 2018
• Grant date: Nov 15, 2022
• Expiry date: Jun 23, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/08
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments are directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements. Thus, the systems and methods described herein beneficially leverage the existing capabilities of on-chip SRAM processor memory circuitry to perform a relatively large number of analog vector/tensor calculations associated with execution of a neural network, such as a recurrent neural network, without burdening the processor circuitry and without significant impact to the processor power requirements.