Three dimensional integrated circuits with stacked transistors

US11605565B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Cheng-Ying Huang
• Willy Rachmady · Beaverton, US
• Gilbert Dewey · Beaverton, US
• Aaron D. Lilak · Beaverton, US
• Kimin Jun · Hillsboro, US
• Brennen Mueller · Portland, US
• Ehren Mannebach · Beaverton, US
• Anh Phan · Beaverton, US
• Patrick Morrow · Portland, US
• Hui Jae Yoo · Hillsboro, US
• Jack T. Kavalieros · Portland, US

Key dates

• Filing date: Dec 28, 2018
• Grant date: Mar 14, 2023
• Expiry date: May 14, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/017

Abstract

Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.