Ferroelectric based latch
US11616507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Jul 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.