III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

US11640961B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Gilbert Dewey · Beaverton, US
• Ravi Pillarisetty · Portland, US
• Jack T. Kavalieros · Portland, US
• Aaron D. Lilak · Beaverton, US
• Willy Rachmady · Beaverton, US
• Rishabh Mehandru · Portland, US
• Kimin Jun · Hillsboro, US
• Anh Phan · Beaverton, US
• Hui Jae Yoo · Hillsboro, US
• Patrick Morrow · Portland, US
• Cheng-Ying Huang
• Matthew V. Metz · Portland, US

Key dates

• Filing date: Mar 28, 2018
• Grant date: May 2, 2023
• Expiry date: Oct 1, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.