Stacked transistors having device strata with different channel widths

US11676966B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Gilbert Dewey · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Willy Rachmady · Beaverton, US
• Cheng-Ying Huang
• Matthew V. Metz · Portland, US
• Kimin Jun · Hillsboro, US
• Patrick Morrow · Portland, US
• Aaron D. Lilak · Beaverton, US
• Ehren Mannebach · Beaverton, US
• Anh Phan · Beaverton, US

Key dates

• Filing date: Mar 15, 2019
• Grant date: Jun 13, 2023
• Expiry date: Sep 16, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/0401
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.