Fabrication of a majority logic gate having non-linear input capacitors

US11742860B2 · kind B2 · utility

Assignee

• Kepler Computing Inc. · US

Inventors

• Sasikanth Manipatruni · Ithaca, US
• Rafael Rios · Portland, US
• Neal Reynolds · Bremerton, US
• Ikenna Odinaka · Durham, US
• Robert Menezes · Portland, US
• Rajeev Kumar Dokania · Beaverton, US
• Ramamoorthy Ramesh · Moraga, US
• Amrita Mathuriya · Portland, US

Key dates

• Filing date: Jun 22, 2022
• Grant date: Aug 29, 2023
• Expiry date: Jun 24, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/694
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.