Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact

US11824116B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Biswajeet Guha · Hillsboro, US
• William Hsu · Hillsboro, US
• Chung-Hsun Lin · White Plains, US
• Kinyip Phoa · Beaverton, US
• Oleg Golonzka · Beaverton, US
• Ayan Kar · Portland, US
• Nicholas A. Thomson · Hillsboro, US
• Benjamin Orr · Munich, DE
• Nathan Jack · Forest Grove, US
• Kalyan C. Kolluru · Portland, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Dec 18, 2019
• Grant date: Nov 21, 2023
• Expiry date: Mar 19, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.