Patent · US Active

Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact

US11837641B2 · kind B2 · utility

0Cited by

2References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Biswajeet Guha · Hillsboro, US
William Hsu · Hillsboro, US
Chung-Hsun Lin · White Plains, US
Kinyip Phoa · Beaverton, US
Oleg Golonzka · Beaverton, US
Tahir Ghani · Portland, US
Kalyan C. Kolluru · Portland, US
Nathan Jack · Forest Grove, US
Nicholas A. Thomson · Hillsboro, US
Ayan Kar · Portland, US
Benjamin Orr · Munich, DE

Key dates

Filing date	Dec 18, 2019
Grant date	Dec 5, 2023
Priority date	—
Expiry date	Apr 3, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/83
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.