Top via with damascene line and via
US11894265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Mar 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.