Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material

US11996404B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Cheng-Ying Huang
• Gilbert Dewey · Beaverton, US
• Ashish Agrawal · Hillsboro, US
• Kimin Jun · Hillsboro, US
• Willy Rachmady · Beaverton, US
• Zachary Geiger · Hillsboro, US
• Cory Bomberger · Portland, US
• Ryan Keech · Portland, US
• Koustav Ganguly · Beaverton, US
• Anand S. Murthy · Beaverton, US
• Jack T. Kavalieros · Portland, US

Key dates

• Filing date: Dec 1, 2021
• Grant date: May 28, 2024
• Expiry date: Dec 1, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0172
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.