Patent · US Active

Cache structure and utilization

US12066975B2 · kind B2 · utility

0Cited by

89References

17Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Altug Koker · Cameron Park, US
Lakshminarayanan Striramassarma · Folsom, US
Aravindh Anantaraman · Folsom, US
Valentin Andrei · San Jose, US
Abhishek R. Appu · Cameron Park, US
Sean Coleman · Brooklyn, US
Varghese George · Folsom, US
K Pattabhiraman · Kanchinakote, IN
Mike B. Macpherson · Portland, US
Subramaniam Maiyuran · Citrus, US
Elmoustapha Ould-Ahmed-Vall · Chandler, US
Vasanth Ranganathan · Cameron Park, US
Joydeep Ray · Folsom, US
S Jayakrishna P · Kanchinakote, IN
Prasoonkumar Surti · Folsom, US

Key dates

Filing date	Mar 14, 2020
Grant date	Aug 20, 2024
Priority date	—
Expiry date	Jun 30, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06T15/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.