Majority gate based low power ferroelectric based adder with reset mechanism
US12088297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2023 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | May 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/694
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.