Apparatus with selectable majority gate and combinational logic gate outputs
US12126339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2022 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Nov 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.