Systolic disaggregation within a matrix accelerator architecture
US12141094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2020 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Dec 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. One embodiment provides techniques to use decompression information when performing sparse compute operations. One embodiment enables the disaggregation of special function compute arrays via a shared reg file. One embodiment enables packed data compress and expand operations on a GPGPU. One embodiment provides techniques to exploit block sparsity within the cache hierarchy of a GPGPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.