Patent · US Active

Systems and methods for error detection and control for embedded memory and compute elements

US12147302B2 · kind B2 · utility

0Cited by

4References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Vasanth Ranganathan · Cameron Park, US
Joydeep Ray · Folsom, US
Abhishek R. Appu · Cameron Park, US
Nikos Kaburlasos · Lincoln, US
Lidong Xu · Beijing, CN
Subramaniam Maiyuran · Citrus, US
Altug Koker · Cameron Park, US
Naveen Matam · Rancho Cordova, US
James M. Holland · Folsom, US
Brent Insko · Portland, US
Sanjeev Jahagirdar · Folsom, US
Scott Janus · Rocklin, US
Durgaprasad Bilagi · Folsom, US
Xinmin Tian · Union City, US

Key dates

Filing date	Nov 11, 2020
Grant date	Nov 19, 2024
Priority date	—
Expiry date	May 26, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/70
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.