Patent · US Active

Bit-cell architecture based in-memory compute

US12183424B2 · kind B2 · utility

0Cited by

5References

33Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventors

Harsh Rawat · Faridabad, IN
Kedar Janardan Dhori · Ghaziabad, IN
Promod Kumar · Misterbianco, IT
Nitin Chawla · Noida, IN
Manuj AYODHYAWASI · Noida, IN

Key dates

Filing date	Sep 27, 2022
Grant date	Dec 31, 2024
Priority date	—
Expiry date	Dec 11, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/54
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.