Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US12237007B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Nov 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.