Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact

US12288789B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Biswajeet Guha · Hillsboro, US
• William Hsu · Hillsboro, US
• Chung-Hsun Lin · White Plains, US
• Kinyip Phoa · Beaverton, US
• Oleg Golonzka · Beaverton, US
• Tahir Ghani · Portland, US
• Kalyan C. Kolluru · Portland, US
• Nathan Jack · Forest Grove, US
• Nicholas A. Thomson · Hillsboro, US
• Ayan Kar · Portland, US
• Benjamin Orr · Munich, DE

Key dates

• Filing date: Jan 9, 2024
• Grant date: Apr 29, 2025
• Expiry date: Jan 9, 2044

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B82Y10/00
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.