Array of vertical transistors and method used in forming an array of vertical transistors

US12336288B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Yi Fang Lee · Boise, US
• Jaydip Guha · Boise, US
• Lars Heineck · Dresden, DE
• Kamal M. Karda · Boise, US
• Si-Woo Lee · Boise, US
• Terrence B. McDaniel · Boise, US
• Scott E. Sills · Boise, US
• Kevin J. Torek · Meridian, US
• Sheng-Wei Yang · Taipei, TW

Key dates

• Filing date: Sep 19, 2022
• Grant date: Jun 17, 2025
• Expiry date: Oct 29, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/80

Abstract

An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual p…