Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode
US12361982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Dec 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.