Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates

US12369392B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Leonard P. GULER · Hillsboro, US
• Michael K. Harper · Hillsboro, US
• William Hsu · Hillsboro, US
• Biswajeet Guha · Hillsboro, US
• Tahir Ghani · Portland, US
• Niels Zussblatt · Hillsboro, US
• Jeffrey Miles Tan · Hillsboro, US
• Benjamin Kriegel · Portland, US
• Mohit K. HARAN · Hillsboro, US
• Reken Patel · Portland, US
• Oleg Golonzka · Beaverton, US
• Mohammad HASAN · Beaverton, US

Key dates

• Filing date: Feb 9, 2024
• Grant date: Jul 22, 2025
• Expiry date: Feb 9, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0147
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.