In-memory computation circuit using static random access memory (SRAM) array segmentation
US12406705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2023 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Nov 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.