Semiconductor device having a low-resistivity planar wiring structure
US5200635A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1991 |
| Grant date | Apr 6, 1993 |
| Priority date | — |
| Expiry date | Apr 17, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.