Plasma-enhanced CVD process using TEOS for depositing silicon oxide

US5362526A · kind A · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• David N. Wang · Saratoga, US
• John M. White · Hayward, US
• Kam S. Law · San Jose, US
• Cissy Leung · Fremont, US
• Salvador P. Umotoy · Pittsburg, US
• Kenneth S. Collins · San Jose, US
• John A. Adamik · San Ramon, US
• Ilya Perlov · Santa Clara, US
• Dan Maydan · Los Altos Hills, US

Key dates

• Filing date: Jan 23, 1991
• Grant date: Nov 8, 1994
• Expiry date: Jan 23, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02216
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge ga…