Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs
US5504029A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1994 |
| Grant date | Apr 2, 1996 |
| Priority date | — |
| Expiry date | Jun 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refract…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.