Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5917211A · kind A · utility
21Cited by
26References
11Claims
0Family size
Assignee
Inventors
- Jun Murata
- Yoshitaka Tadaki
- Hiroko Kaneko
- Toshihiro Sekiguchi
- Hiroyuki Uchiyama
- Hisashi Nakamura
- Toshio Maeda
- Osamu Kasahara
- Hiromichi Enami
- Atsushi Ogishima
- Masaki Nagao
- Michimasa Funabashi
- Yasuo Kiguchi
- Masayuki Kojima
- Atsuyoshi Koike
- Hiroyuki Miyazawa
- Masato Sadaoka
- Kazuya Kadota
- Tadashi Chikahara
- Kazuo Nojiri
- Yutaka Kobayashi
Key dates
| Filing date | Nov 25, 1997 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Nov 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0133
Abstract
A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.