Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices

US6025240A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Vei-Han Chan · San Jose, US
• Scott Luning · San Francisco, US
• Mark Randolph · San Jose, US
• Nicholas H. Tripsas · San Jose, US
• Daniel Sobek · Loveland, US
• Janet Wang · San Francisco, US
• Timothy Thurgate · Sunnyvale, US
• Sameer Haddad · San Jose, US

Key dates

• Filing date: Dec 18, 1997
• Grant date: Feb 15, 2000
• Expiry date: Dec 18, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0411

Abstract

A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least…