Apparatus for testing semiconductor wafers

US6064216A · kind A · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Warren M. Farnworth · Nampa, US
• Salman Akram · Boise, US
• Alan G. Wood · Boise, US
• David R. Hembree · Boise, US
• James M. Wark · Boise, US
• John O. Jacobson · Boise, US

Key dates

• Filing date: Feb 1, 1999
• Grant date: May 16, 2000
• Expiry date: Feb 1, 2019

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2886
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.