Thin resist with amorphous silicon hard mask for via etch application
US6165695A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Dec 1, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S430/168
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.