Method using a thin resist mask for dual damascene stop layer etch

US6184128A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Fei Wang · San Jose, US
• Christopher F. Lyons · Fremont, US
• Khanh B. Nguyen · San Mateo, US
• Scott A. Bell · San Jose, US
• Harry J. Levinson · Saratoga, US
• Chih-Yuh Yang · San Jose, US

Key dates

• Filing date: Jan 31, 2000
• Grant date: Feb 6, 2001
• Expiry date: Jan 31, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31144
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second photoresist have a thickness of about 1,500 .ANG. or less.