Selective damascene chemical mechanical polishing
US6261157A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 1999 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | May 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A selective Damascene chemical mechanical polishing (CMP) technique is used to planarize a semiconductor device to remove surface topography. The semiconductor device includes a semiconductor layer formed on a substrate, an insulating layer formed over the semiconductor layer and patterned to expose a portion of the semiconductor layer, a barrier layer formed over the insulating layer and the exposed portion of the semiconductor layer, and an electrically conductive layer formed over the barrier layer. The semiconductor device is pressed against a first rotating polishing pad that has no embedded abrasive particles to remove a portion of the conductive layer that overlies both the barrier layer and the insulating layer. The semiconductor device is then pressed against a second rotating polishing pad that has embedded abrasive particles to expose a portion of the barrier layer that overlies the insulating layer. The device is then pressed against a third rotating polishing pad that has no embedded abrasive particles to remove the portion of the barrier layer that overlies the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.