Segmented architecture for wafer test and burn-in

US6275051A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Thomas W. Bachelder · Holly Springs, US
• Dennis R. Barringer · Wallkill, US
• Dennis R. Conti · South Burlington, US
• James M. Crafts · Warren, US
• David L. Gardell · Saint Albans, US
• Paul M. Gaschke · Beacon, US
• Mark R. LaForce · South Burlington, US
• Charles H. Perry · Poughkeepsie, US
• Roger R. Schmidt · Poughkeepsie, US
• Joseph J. Van Horn · Underhill, US
• Wade H. White · Hyde Park, US

Key dates

• Filing date: Jan 29, 1999
• Grant date: Aug 14, 2001
• Expiry date: Jan 29, 2019

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2863
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.