Method to form a low parasitic capacitance pseudo-SOI CMOS device
US6403485B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2001 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | May 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.