Simultaneous formation of charge storage and bitline to wordline isolation

US6465306B1 · kind B1 · utility

Assignees

• Advanced Micro Devices, Inc. · US
• FUJITSU LIMITED · JP

Inventors

• Mark T. Ramsbey · Sunnyvale, US
• Jean Y. Yang · Sunnyvale, US
• Hidehiko Shiraiwa · San Jose, US
• Michael A. Van Buskirk · Saratoga, US
• David Michael Rogers · Sunnyvale, US
• Ravi Sunkavalli · Santa Clara, US
• Janet Wang · San Francisco, US
• Narbeh Derhacobian · Belmont, US
• Yider Wu · Campbell, US

Key dates

• Filing date: Nov 28, 2000
• Grant date: Oct 15, 2002
• Expiry date: Nov 29, 2020

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/981

Abstract

One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.