Method to form and/or isolate vertical transistors

US6511884B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Elgin Quek · Singapore, SG
• Ravi Sundaresan · San Jose, US
• Yang Pan · Singapore, SG
• Yong Meng Lee · Singapore, SG
• Ying-Keung Leung · Hong Kong, CN
• Yelehanka Ramachandramurthy Pradeep · Singapore, SG
• Jia Zhen Zheng · Singapore, SG
• Lap Chan · San Francisco, US

Key dates

• Filing date: Oct 9, 2001
• Grant date: Jan 28, 2003
• Expiry date: Oct 9, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/63

Abstract

A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a s…