Planar structure for non-volatile memory devices

US6541816B2 · kind B2 · utility

Assignees

• Advanced Micro Devices, Inc. · US
• FUJITSU LIMITED · JP

Inventors

• Mark T. Ramsbey · Sunnyvale, US
• Jean Y. Yang · Sunnyvale, US
• Hidehiko Shiraiwa · San Jose, US
• Michael A. Van Buskirk · Saratoga, US
• David Michael Rogers · Sunnyvale, US
• Ravi Sunkavalli · Santa Clara, US
• Janet Wang · San Francisco, US
• Narbeh Derhacobian · Belmont, US

Key dates

• Filing date: Jun 27, 2001
• Grant date: Apr 1, 2003
• Expiry date: Jun 27, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/981

Abstract

One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.